Temperature detecting semiconductor device

ABSTRACT

There is provided a technique which is capable of detecting a temperature of a semiconductor device with high precision. A temperature detection circuit detecting a temperature of a semiconductor device includes a first short-cycle oscillator generating a first clock signal having positive temperature characteristics with respect to a frequency, a second short-cycle oscillator generating a second clock signal having negative temperature characteristics with respect to the frequency, and a temperature signal generation unit generating a temperature signal which is varied according to the temperature of the semiconductor device based on the first and second clock signals.

CROSS-REFERENCED APPLICATION

The present application is a continuation of application Ser. No.11/452,317, filed Jun. 14, 2006, which claims priority under 35 USC §119 to Japanese Application No. 2005-177415, filed Jun. 17, 2005 andJapanese Application No. 2006-060651, filed Mar. 7, 2006.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor device having atemperature detection function.

2. Description of the Background Art

Recently, semiconductor technology is miniaturized in order to implementfurther high speed and high integration of a semiconductor integratedcircuit. Accordingly, an effect that a temperature variation has ondevice characteristics becomes apparent, and it is necessary toappropriately control the characteristics according to the temperatureso that the device may not be erroneously operated by the temperaturevariation. Thus, it is necessary to correctly detect a temperature ofthe device, and various kinds of temperature detection circuits havebeen proposed conventionally. For example, Japanese Patent ApplicationLaid-Open Nos. 2000-55742, 58-35431 (1983), 05-307882 (1993), 09-223395(1997), 2000-269417 and 10-239097 (1998) disclose a temperaturedetection circuit which detects a temperature of a semiconductor devicebased on a variation of a frequency of a clock signal with temperature.

However, sufficient temperature detection precision cannot be providedin the conventional temperature detection circuit, so that an erroneousoperation of the device due to a temperature variation could not becompletely prevented.

Meanwhile, since the characteristics of the device is varied due to avariation in manufacturing process, when the characteristics of thedevice is adjusted based on a temperature detection result, it isimportant to note that they are not affected by the variation inmanufacturing process.

SUMMARY OF THE INVENTION

It is a first object of the present invention to provide a techniquewhich is capable of detecting a temperature of a semiconductor devicewith high precision. In addition, it is a second object of the presentinvention to provide a technique which is capable of appropriatelyadjusting device characteristics based on a temperature detection resultwithout being affected by a variation in manufacturing process.

A first semiconductor device according to the present invention includesfirst and second oscillators and a temperature signal generationcircuit. The first oscillator generates a first clock signal havingpositive temperature characteristics with respect to a frequency. Thesecond oscillator generating a second clock signal having negativetemperature characteristics with respect to a frequency. The temperaturesignal generation unit generates a temperature signal which is variedaccording to a temperature of the first semiconductor device based onthe first and second clock signals.

The temperature signal which is varied according to the temperature ofthe semiconductor device is generated based on the first clock signalhaving the positive temperature characteristics with respect to thefrequency and the second clock signal having the negative temperaturecharacteristics with respect to the frequency. Therefore, since thetemperature signal which is sensitively varied according to thetemperature of the semiconductor device is capable of being generated,temperature detection precision is improved.

A second semiconductor device according to the present inventionincludes a temperature detection circuit detecting a temperature of thesecond semiconductor device, an object circuit whose electricalcharacteristics are adjusted, and a tuning circuit adjusting theelectrical characteristics of the object circuit based on a detectionresult in the temperature detection circuit. The tuning circuit includesa memory circuit and a tuning code selection circuit. The memory circuitstores a plurality of tuning codes for adjusting the electricalcharacteristics of the object circuit, in which memory information iscapable of being rewritten. The tuning code selection circuit selectsone of the tuning codes based on a detection result in the temperaturedetection circuit and outputs it to the object circuit.

Since the plurality of tuning codes for adjusting the electricalcharacteristics of the object circuit are stored in the memory circuitin which the memory information is capable of being rewritten, thetuning codes are capable of being rewritten. Therefore, even when theelectrical characteristics of the object circuit are varied due to thevariation in manufacturing process, the tuning codes are capable ofbeing rewritten to appropriate values according to the variation. Thus,the electrical characteristics of the object circuit are capable ofbeing appropriately adjusted based on the temperature detection resultwithout being affected by the variation in manufacturing process.

These and other objects, features, aspects and advantages of the presentinvention will become more apparent from the following detaileddescription of the present invention when taken in conjunction with theaccompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram showing a constitution of a semiconductordevice according to a first embodiment of the present invention;

FIG. 2 is a block diagram showing a constitution of a temperaturedetection unit according to the first embodiment of the presentinvention;

FIG. 3 is a timing chart showing an operation of a temperature detectioncircuit according to the first embodiment of the present invention;

FIG. 4 is a view showing temperature characteristics with respect to afrequency of a short-cycle oscillator according to the first embodimentof the present invention;

FIG. 5 is a circuit diagram showing a constitution of the short-cycleoscillator showing positive temperature characteristics according to thefirst embodiment of the present invention;

FIG. 6 is a circuit diagram showing a constitution of the short-cycleoscillator showing negative temperature characteristics according to thefirst embodiment of the present invention;

FIG. 7 is a circuit diagram showing another constitution of theshort-cycle oscillator showing negative temperature characteristicsaccording to the first embodiment of the present invention;

FIG. 8 is a block diagram showing constitutions of a tuning circuit andan inner power supply circuit according to the first embodiment of thepresent invention;

FIG. 9 is a circuit diagram showing a constitution of a selectioncircuit in the tuning circuit according to the first embodiment of thepresent invention;

FIG. 10 is a block diagram showing a constitution of a temperaturedetection circuit to be compared with the present invention;

FIG. 11 is a timing chart showing an operation of the temperaturedetection circuit to be compared with the present invention;

FIG. 12 is a view showing a temperature characteristics with respect toa frequency of the short-cycle oscillator in the temperature detectioncircuit to be compared with the present invention;

FIG. 13 is a block diagram showing a constitution of a temperaturedetection circuit according to a second embodiment of the presentinvention;

FIG. 14 is a timing chart showing an operation of the temperaturedetection circuit according to the second embodiment of the presentinvention;

FIG. 15 is a block diagram showing a constitution of a timing generationcircuit according to a third embodiment of the present invention;

FIG. 16 is a block diagram showing a constitution of a clock signalgeneration circuit according to a fourth embodiment of the presentinvention;

FIG. 17 is a block diagram showing constitutions of a tuning circuit andan inner power supply circuit according to a fifth embodiment of thepresent invention;

FIG. 18 is a flowchart showing a method of setting tuning codesaccording to the fifth embodiment of the present invention;

FIG. 19 is a graph showing that temperature characteristics of areference voltage generation circuit are varied due to a variation inmanufacturing process;

FIG. 20 is a view showing code values of the tuning codes to be preparedin view of the variation in manufacturing process; and

FIG. 21 is a circuit diagram showing a constitution of a referencevoltage generation circuit according to a sixth embodiment of thepresent invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment

FIG. 1 is a block diagram showing a constitution of a semiconductordevice according to a first embodiment of the present invention. Asshown in FIG. 1, the semiconductor device according to the firstembodiment includes a temperature detection unit 10, a tuning circuit20, an inner power supply circuits 30 and 50, a memory circuit 40, and alogic circuit 60. These components are formed on a single semiconductorsubstrate 1 and the semiconductor substrate 1 is housed in a resinpackage 100.

The temperature detection unit 10 detects a temperature T of thesemiconductor device, and outputs its result as a temperature signalTEMP. The tuning circuit 20 generates an adjustment signal TNS based onthe temperature signal TEMP outputted from the temperature detectionunit 10 and supplies the adjustment signal TNS to the inner power supplycircuits 30 and 50 so as to adjust their characteristics.

The inner power supply circuit 30 is a step-down power supply circuit,for example. The inner power supply circuit 30 generates an inner powersupply voltage VCCM to be used as a power supply voltage of the memorycircuit 40, from an outer power supply voltage VCC inputted from theoutside of the resin package 100, and outputs the inner power supplyvoltage VCCM. The inner power supply circuit 30 is capable of outputtinga constant power supply voltage VCCM when the outer power supply voltageVCC is within a predetermined range. Therefore, even when the outerpower supply voltage VCC fluctuates to some extent, the inner powersupply voltage VCCM is capable of being stably outputted. In addition,the inner power supply circuit 30 outputs the inner power supply voltageVCCM which corresponds to the inputted adjustment signal TNS. Thus, theinner power supply voltage VCCM is automatically adjusted according tothe temperature T.

The inner power supply circuit 50 is a step-down power supply circuitsimilar to the inner power supply circuit 30 and generates an innerpower supply voltage VCCL to be used as a power supply voltage of thelogic circuit 60 from the outer power supply voltage VCC and outputs it.The inner power supply circuit 50 is capable of outputting a constantpower supply voltage VCCL when the outer power supply voltage VCC iswithin a predetermined range. Therefore, even when the outer powersupply voltage VCC fluctuates to some extent, the inner power supplyvoltage VCCL is capable of being stably outputted. In addition, theinner power supply circuit 50 outputs the inner power supply voltageVCCL which corresponds to the inputted adjustment signal TNS. Thus, theinner power supply voltage VCCL is automatically adjusted according tothe temperature T. According to the first embodiment, the inner powersupply voltage VCCM and the inner power supply voltage VCCL are set todifferent voltage values.

The memory circuit 40 is a DRAM (Dynamic Random Access Memory), forexample and includes a plurality of memory cells and peripheral circuits(not shown). The memory circuit 40 is operated by the inner power supplyvoltage VCCM outputted from the inner power supply circuit 30. The logiccircuit 60 includes a plurality of logic elements such as an AND circuitand an OR circuit and executes various logical operations. The logiccircuit 60 is operated by the inner power supply voltage VCCL outputtedfrom the inner power supply circuit 50.

FIG. 2 is a block diagram showing a constitution of the temperaturedetection unit 10. As shown in FIG. 2, the temperature detection unit 10includes a temperature detection timing control circuit 11 and atemperature detection circuit 14. The temperature detection timingcontrol circuit 11 includes a long-cycle oscillator 12 and a timingpulse generation circuit 13 and controls an execution timing of thetemperature detection in the temperature detection circuit 14. Thelong-cycle oscillator 12 outputs a clock signal CLK0 having a cycle ofseveral .mu.sec. Since the clock signal CLK0 has stable temperaturecharacteristics with respect to a frequency, even when the temperature Tof the semiconductor device is varied, its frequency is hardly varied.

The timing pulse generation circuit 13 sequentially generates aplurality of timing pulse signals TPS based on the clock signal CLK0outputted from the long-cycle oscillator 12 and outputs them to thetemperature detection circuit 14. The timing pulse generation circuit 13generates the timing pulse signals TPS having a predetermined pulsewidth at predetermined intervals and can control the pulse width and thegeneration intervals of the timing pulse signals TPS.

For example, the timing pulse generation circuit 13 counts the number ofpulses of the clock signal CLK0 and when the counted number reaches afirst reference value, it changes a Low-level signal to a High-levelsignal and then the number of pulses of the clock signal CLK0 is newlycounted and when the newly counted number reaches a second referencevalue, the High-level signal is changed to the Low-level signal. Then,the number of pulses of the clock signal CLK0 is newly counted again andwhen the newly counted number reaches the first reference value, theLow-level signal is changed to the High-level signal again. Thus, thetiming pulse signals TPS having the predetermined width are capable ofbeing generated at predetermined intervals by counting the number ofpulses of the clock signal CLK0, and the pulse width and the generationintervals of the timing pulse signals TPS are capable of beingindividually controlled by varying the first and second reference valuesto be compared with the counted number individually. In addition, thetiming pulse generation circuit 13 determines the first and secondreference values according to an instruction from a CPU (not shown)provided in the semiconductor device.

The temperature detection circuit 14 includes a short-cycle oscillators15 and 16 and a temperature signal generation circuit 17, and generatesa temperature signal TEMP every time the timing pulse signal TPS isinputted and outputs it to the tuning circuit 20. The short-cycleoscillator 15 generates a clock signal CLK1 having a positivetemperature characteristics with respect to the frequency. Therefore, afrequency f1 of the clock signal CLK1 increases as the temperature T ofthe semiconductor device rises and decreases as the temperature T falls.Meanwhile, the short-cycle oscillator 16 generates a clock signal CLK2having a negative temperature characteristics with respect to thefrequency. Therefore, a frequency f2 of the clock signal CLK2 decreasesas the temperature T of the semiconductor device rises and increases asthe temperature T falls. In addition, the cycles of the clock signalsCLK1 and CLK2 are set sufficiently smaller than the that of the clocksignal CLK0.

The temperature signal generation circuit 17 includes counters 18 and 19and generates a temperature signal TEMP which is varied according to thetemperature T of the semiconductor device, based on the clock signalsCLK1 and CLK2. The counter 18 counts the number of pulses of the clocksignal CLK1 by a predetermined number N and outputs a count periodsignal CPS which is activated during the counting period. The counter 19counts the number of pulses of the clock signal CLK2 while the countperiod signal CPS is activated and outputs a signal showing the countednumber M to the tuning circuit 20 as the temperature signal TEMP.

FIG. 3 is a timing chart showing an operation of the temperaturedetection circuit 14. As shown in FIG. 3, when the timing pulse signalTPS rises, the short-cycle oscillator 15 and the counter 18 areactivated. Then, the short-cycle oscillator 15 oscillates and outputsthe clock signal CLK1 and the counter 18 counts the number of pulses ofthe clock signal CLK1 by the number N and outputs a pulse signal whichbecomes High level while the number is counted as the count periodsignal CPS. When the count period signal CPS falls, the short-cycleoscillator 15 and the counter 18 stops their operation. Then, when thetiming pulse signal TPS rises again, the short-cycle oscillator 15 andthe counter 18 are activated and the same operation as the above isrepeated.

The short-cycle oscillator 16 and the counter 19 are activated when thecount period signal CPS rises, and the short-cycle oscillator 16oscillates and outputs the clock signal CLK2 and the counter 19 countsthe number of pulses of the clock signal CLK2 while the count periodsignal CPS is at High level and outputs a signal showing the countednumber M as the temperature signal TEMP. The short-cycle oscillator 15and the counter 18 stop their operation when the count period signal CPSfalls and then when the count period signal CPS rises again, the sameoperation as the above is executed.

As described above, according to the temperature detection circuit 14 inthe first embodiment, while the number of pulses of the clock signalCLK1 is counted to the number N, the number of pulses of the clocksignal CLK2 is counted to the number M. Therefore, when N=M, thefrequencies f1 and f2 of the clock signals CLK1 and CLK2 are such thatf1=f2 and when N>M, they are such that f1>f2 and when N<M, they are suchthat f1<f2.

FIG. 4 is a view showing a relation between the temperature T of thesemiconductor device and the frequencies f1 and f2 of the clock signalsCLK1 and CLK2. According to the first embodiment, the frequencies f1 andf2 of the clock signals CLK1 and CLK2 when the temperature T is a roomtemperature T0 are set to the same value. As shown in FIG. 4, when thetemperature T rises, the frequency f1 showing the positive temperaturecharacteristics increases and the frequency f2 showing the negativetemperature characteristics decreases. Thus, when the temperature Tbecomes higher than the room temperature T0, the frequency f1 becomeshigher than the frequency f2 and a difference between them increases asthe temperature T becomes high.

Meanwhile, when the temperature T falls, the frequency f1 showing thepositive temperature characteristics decreases and the frequency f2showing the negative temperature characteristics increases. Thus, whenthe temperature T becomes lower than the room temperature T0, thefrequency f1 becomes lower than the frequency f2 and a differencebetween them increases as the temperature T becomes low.

Thus, when T>T0, f1>f2, so that when T>T0, N>M. Meanwhile, when T<T0,f1<f2, so that when T<T0, N<M. According to the first embodiment, sincethe value N is a constant value and it is not changed, the value of thepresent temperature T can be found by previously finding the relationbetween the temperature T and the counted number M through simulationand the like and referring the temperature signal TEMP showing thecounted number M.

Next, a circuit constitution example of the short-cycle oscillator 15having the positive temperature characteristics will be described. FIG.5 is a circuit diagram showing one example of a constitution of theshort-cycle oscillator 15. The short-cycle oscillator 15 shown in FIG. 5is a current control type of oscillator which is operated by the innerpower supply voltage VCCL and includes a NAND circuit 150 and pluralstages of inversion circuits 151. Each of the inversion circuits 151includes a PMOS transistor 151 a and NMOS transistors 151 b and 151 c.The inner power supply voltage VCCL is applied to a source of the PMOStransistor 151 a and a drain of the NMOS transistor 151 b is connectedto a drain of the PMOS transistor 151 a. A drain of the NMOS transistor151 c is connected to a source of the NMOS transistor 151 b, and aground voltage is applied to a source of the NMOS transistor 151 c.Thus, a gate of the PMOS transistor 151 a and a gate of the NMOStransistor 151 b are connected to each other.

In each of the inversion circuits 151 except for the last stage ofcircuit 151, a connection point between the drain of the PMOS transistor151 a and the drain of the NMOS transistor 151 b is connected to aconnection point between a gate of the PMOS transistor 151 a and a gateof the NMOS transistor 151 b in the next inversion circuit 151. In thelast inversion circuit 151, a signal at the connection point between adrain of the PMOS transistor 151 a and a drain of the NMOS transistor151 b is outputted as the clock signal CLK1 and the connection point isconnected to one input of the NAND circuit 150.

An activation signal ACT is inputted to the other input of the NANDcircuit 150 and an output of the NAND circuit 150 is connected to aconnection point between the gate of the PMOS transistor 151 a and thegate of the NMOS transistor 151 b in the first stage of inversioncircuit 151. A bias voltage BIAS is inputted to each of the gates of theNMOS transistor 151 c in the plural stages of inversion circuits 151.

According to the circuit shown in FIG. 5, when the activation signal ACTis shifted from Low level to High level, oscillation of the clock signalCLK1 is started and when it is shifted from High level to Low level, theoscillation of the clock signal CLK1 is stopped. Therefore, theshort-cycle oscillator 15 which performs the above operation can beprovided by adding a circuit which generates a signal which becomes Highlevel when the timing pulse signal TPS becomes High level, and becomesLow level when the count period signal CPS becomes Low level, to theconstitution in FIG. 5, and inputting that signal to the NAND circuit150 as the activation signal ACT.

In addition, when the bias voltage BIAS is varied, since an outputcurrent of the inversion circuit 151 is varied, the temperaturecharacteristics of the short-cycle oscillator 15 can be adjusted by thebias voltage BIAS. Therefore, the short-cycle oscillator 15 having thepositive temperature characteristics shown in FIG. 4 can be implementedby appropriately setting the bias voltage BIAS.

Next, a circuit constitution example of the short-cycle oscillator 16having the negative temperature characteristics will be described. FIG.6 is a circuit diagram showing one example of the constitution of theshort-cycle oscillator 16, and FIG. 7 is a circuit diagram showinganother constitution of the short-cycle oscillator 16. The short-cycleoscillator 16 shown in FIG. 6 is an inverter type of oscillator which isoperated by the inner power supply voltage VCCL, and includes a NANDcircuit 160 and plural stages of CMOS inverter circuits 161. The countperiod signal CPS is inputted to one input of the NAND circuit 160 andan output of the last stage of CMOS inverter circuit 161 is connected tothe other input thereof. An output of the NAND circuit 160 is connectedto an input of the first stage of CMOS inverter circuit 161. In theplural stages of CMOS inverter circuits 161 except for the last stagethereof, respective outputs are connected to inputs of the next CMOSinverter circuit 161. An output signal of the last stage of CMOSinverter circuit 161 is outputted to the counter 19 as the clock signalCLK2.

According to the short-cycle oscillator 16 shown in FIG. 7, a pluralityof RC delay circuits 162 are added to the circuit constitution shown inFIG. 6. The plurality of RC delay circuits 162 correspond to theplurality of CMOS inverter circuits 161 one on one, and they areprovided at the input stage of the corresponding CMOS inverter circuit161. The RC delay circuit 162 includes a resistor element R and acapacitor element C. One end of the capacitor element C is connected toone end of the resistor element R and an input of the corresponding CMOSinverter circuit 161, and the ground voltage is applied to the other endof the capacitor C. Furthermore, the other end of the resistor element Ris connected to an output of the previous element.

In the short-cycle oscillator 16 shown in FIG. 6 or 7, when the countperiod signal CPS is shifted from Low level to High level, oscillationof the clock signal CLK2 is started and when it is shifted from Highlevel to Low level, the oscillation of the clock signal CLK2 is stopped.

In addition, as shown in FIG. 4, according to the frequency f2 of theshort-cycle oscillator 16 shown in FIG. 6 or 7, an absolute value ofvariation with respect to the temperature T is small as compared withthe frequency f1 of the short-cycle oscillator 15 shown in FIG. 5. Thatis, the frequency f2 of the short-cycle oscillator 16 shown in FIG. 6 or7 is not varied so much by the temperature T as the frequency f1 of theshort-cycle oscillator 15 shown in FIG. 5. In addition, according to theshort-cycle oscillator 16 shown in FIG. 7, its temperaturecharacteristics can be adjusted in some degree by varying the value ofthe resistor element R or the capacitor element C of the RC delaycircuit 162.

FIG. 8 is a block diagram showing constitutions of the tuning circuit 20and the inner power supply circuit 30. In addition, since a constitutionof the inner power supply circuit 50 is the same as that of the innerpower supply circuit 30, its description will be omitted. As shown inFIG. 8, the tuning circuit 20 includes a tuning code memory circuit 21in which n (.gtoreq.2) tuning codes CC1 to CCn are stored, and a tuningcode selection circuit 22 which selects one code from the plurality oftuning codes CC1 to CCn according to the temperature signal TEMPoutputted from the temperature detection unit 10 and outputs it.

The tuning code memory circuit 21 is a register circuit configured by aplurality of flip flops or a fuse circuit using a metal fuse or anelectric fuse, for example, and its memory information is capable ofbeing rewritten by the above-described CPU (not shown). Thus, the tuningcode memory circuit 21 outputs all of the stored plurality of tuningcodes CC1 to CCn to the tuning code selection circuit 22.

The tuning code selection circuit 22 includes a selection signalgeneration circuit 23 generating a selection signal group SELG which isvaried according to the temperature signal TEMP, and a selection circuit24 selecting one code from the plurality of tuning codes CC1 to CCnbased on the selection signal group SELG generated in the selectionsignal generation circuit 23 and outputs it as the adjustment signalTNS.

According to the first embodiment, a range of the values of thetemperature signal TEMP, that is, a range of the counted values of thecounter 19 is presorted to n sections whose number is the same as thatof the tuning codes CC1 to CCn, and the selection signal generationcircuit 23 determines which section the inputted temperature signal TEMPbelongs to. The selection signal group SELG includes n selection signalsSEL<0> to SEL<n−1>, and these selection signals SEL<0> to SEL<n−1>correspond to the above n sections one on one. The selection signalgeneration circuit 23 sets the value of the signal corresponding to thesection the received temperature signal TEMP belongs to, to “1” amongthe selection signals SEL<0> to SEL<n−1> and outputs the selectionsignal group SELG to the selection circuit 24.

For example, when it is assumed that the counter 19 is a three-bitcounter and the temperature signal TEMP includes 3-bit data TEMP<2:0>,the value of the temperature signal TEMP ranges from “000” to “111” (“0”to “7” in decimal form). This range is divided into a range from “000”to “100” (referred to as the “section A” hereinafter) and a range from“101” to “101” (referred to as the “section B” hereinafter), for exampleand the selection signal SEL<0> corresponds to the section A and theselection signal SEL<1> corresponds to the section B of the twoselection signals SEL<0> and SEL<1> of the selection signal group SELG,for example. In this case, when the value of the received temperaturesignal TEMP is “010” and belongs to the section A, the selection signalgeneration circuit 23 outputs a selection signal group SELG in which theselection signal SEL<0> designates “1” and the selection signal SEL<1>designates “0”. FIG. 9 is a circuit diagram showing a constitution ofthe selection signal generation circuit 23 in this case.

The selection signal generation circuit 23 shown in FIG. 9 includes aNAND circuit 230, an AND circuit 231 and an OR circuit 232. The NANDcircuit 230 calculates negative AND between an inverted value of thedata TEMP<0> and an inverted value of the data TEMP<1> and outputs it tothe AND circuit 231. The AND circuit 231 calculates logical AND betweenthe output of the NAND circuit 230 and the data TEMP<2> and outputs itas the selection signal SEL<1>. The OR circuit 232 calculates logical ORbetween an inverted value of the output of the NAND circuit 230 and aninverted value of the data TEMP<2> and outputs it as the selectionsignal SEL<0>.

According to the selection signal generation circuit 23 having the abovecircuit constitution, when the data TEMP<2:0> ranges from “000” to“100”, the selection signal SEL<1>=0 and the selection signal SEL<0>=1,and when the data TEMP<2:0> ranges from “101” to “111”, the selectionsignal SEL<1>=1 and the selection signal SEL<0>=0.

The plurality of tuning codes CC1 to CCn stored in the tuning codememory circuit 21 correspond to the n selection signals SEL<0> toSEL<n−1> of the selection signal group SELG one on one. The selectioncircuit 24 selects the code corresponding to the signal designating “1”among the selection signals SEL<0> to SEL<n−1> from the plurality oftuning codes CC1 to CCn and outputs it as the adjustment signal TNS.

The inner power supply circuit 30 includes a reference voltagegeneration circuit 31 generating a reference voltage VREF and outputtingit and an inner voltage generation circuit 32 generating an inner powersupply voltage VCCM from the reference voltage VREF and outputting it.The reference voltage generation circuit 31 can vary a value of thereference voltage VREF to n kinds and the n kinds of voltage valuescorrespond to the n tuning codes CC1 to CCn one on one. The referencevoltage generation circuit 31 outputs the reference voltage VREF showingthe voltage value corresponding to the tuning code designated by theinputted adjustment signal TNS.

The inner voltage generation circuit 32 generates the inner power supplyvoltage VCCM, for example, having the same value as that of thereference voltage VREF and outputs it. Therefore, when the referencevoltage VREF is varied according to the adjustment signal TNS, the innerpower supply voltage VCCM is also varied. Here, the adjustment signalTNS is varied according to the temperature signal TEMP as can beunderstood from the above description. Therefore, the inner power supplyvoltage VCCM is also varied according to the temperature signal TEMP.Thus, the value of the inner power supply voltage VCCM is appropriatelyadjusted according to the temperature T of the semiconductor device. Inaddition, the reference voltage VREF may be supplied to a circuit (notshown) other than the inner voltage generation circuit 32.

As described above, the temperature detection circuit 14 according tothe first embodiment generates the temperature signal TEMP which isvaried according to the temperature T of the semiconductor device of thepresent invention based on the clock signal CLK1 having the positivetemperature characteristics with respect to the frequency and the clocksignal CLK2 having the negative temperature characteristics with respectto the frequency. Therefore, since the temperature signal TEMP which issensitively varied according to the temperature T of the semiconductordevice is capable of being generated, temperature detection precision isimproved. This effect will be described in detail hereinafter.

FIG. 10 is a block diagram showing a constitution of a temperaturedetection circuit 114 to be compared with the temperature detectioncircuit 14 according to the first embodiment. The temperature detectioncircuit 114 shown in FIG. 10 is different from the temperature detectioncircuit 14 in that it generates a temperature signal TEMP only using theclock signal CLK1 having the positive temperature characteristics.

As shown in FIG. 10, the temperature detection circuit 114 includes theabove-described short-cycle oscillator 15 and a counter 118. The counter118 counts the number of pulses of the clock signal CLK1 while a timingpulse signal TPS is activated and outputs a signal showing the countednumber N as the temperature signal TEMP.

FIG. 11 is a timing chart showing an operation of the temperaturedetection circuit 114. As shown in FIG. 11, when the timing pulse signalTPS rises, the short-cycle oscillator 15 and the counter 118 areactivated. Then, the short-cycle oscillator 15 oscillates and outputsthe clock signal CLK1, and the counter 118 starts to count the number ofpulses of the clock signal CLK1. Then, when the timing pulse signal TPSfalls, the short-cycle oscillator 15 stops its operation and the counter118 stops counting the number of pulses and outputs the counted number Nat that time as the temperature signal TEMP. Then, when the timing pulsesignal TPS rises again, the same operation as the above is repeated.

FIG. 12 is a view showing a relation between a temperature T and afrequency f1 of the clock signal CLK1 in the case where the temperaturedetection circuit 114 is incorporated instead of the temperaturedetection circuit 14 in the semiconductor device according to the firstembodiment. As shown in FIG. 12, when it is assumed that the frequencyf1 of the clock signal CLK1 is f0 when the temperature T is a roomtemperature T0, in a case where the temperature T becomes higher thanthe room temperature T0, the frequency f1 showing the positivetemperature characteristics becomes higher than the f0. Meanwhile, in acase where the temperature T becomes lower than the room temperature T0,the frequency f1 becomes lower than the f0.

Thus, when T>T0, the frequencies are such that f1>f0, so that when it isassumed that the counted number N of the counter 118 when T=T0 is N0,the numbers are such that N>N0 when T>T0. Meanwhile, when T<T0, thefrequencies are such that f1<f0, so that the numbers are such that N<N0when T<T0. Therefore, the value of the present temperature T can befound by previously finding the relation between the temperature T andthe counted number N through simulation and the like and referring thetemperature signal TEMP.

As described above, the temperature T can be detected only by using theclock signal CLK1. However, even when the temperature T is varied, sincethe frequency is hardly varied while the timing pulse signal TPS is atHigh level, only the counted number N of the counter 118 is variedaccording to the temperature T. That is, the temperature signal TEMP isvaried only depending on the temperature characteristics of the clocksignal CLK1.

Meanwhile, according to the temperature detection circuit 14 in thefirst embodiment, since the count period signal CPS is generated basedon the clock signal CLK1 having the positive temperaturecharacteristics, the pulse width of the count period signal CPS isvaried according to the temperature T. Thus, when the temperature T isvaried, the frequency of the clock signal CLK2 is varied in thedirection opposite to the direction in which the pulse width of thecount period signal CPS is varied. Therefore, the counted number M ofthe counter 19, that is, the value of the temperature signal TEMPbecomes small as the temperature T becomes high and then the pulse widthof the count period signal CPS is shortened, and becomes small as thefrequency of the clock signal CLK2 becomes low. Meanwhile, as thetemperature T becomes low, the value of the temperature signal TEMPbecomes great because the pulse width of the count period signal CPS iselongated and becomes great because the frequency of the clock signalCLK2 becomes high.

Thus, according to the temperature detection circuit 14 in the firstembodiment, since the temperature signal TEMP is varied depending onboth clock signals CLK1 and CLK2, the temperature signal TEMP issensitively varied with respect to the temperature T. As a result, thetemperature detection precision is improved.

In addition, according to the first embodiment, since the electriccharacteristics of the circuit to be adjusted such as the inner powersupply circuit 30 or 50 are adjusted based on the temperature signalTEMP which can be sensitively varied with respect to the temperature T,the characteristics can be adjusted with respect to the temperaturevariation with high precision. As a result, an erroneous operation ofthe semiconductor device of the present invention can be surelyprevented.

In addition, according to the temperature detection unit 10 in the firstembodiment, the temperature detection timing control circuit 11 cancontrol generation intervals of the plurality of timing pulse signalsTPS, and the temperature detection circuit 14 generates the temperaturesignal TEMP every time one of the plurality of timing pulse signals TPSis inputted. Therefore, an execution timing of the temperature detectionin the temperature detection circuit 14 can be controlled by controllingthe generation intervals of the plurality of timing pulse signals TPS.Thus, an optimal temperature detection execution timing corresponding toa system in which the semiconductor device of the present invention isused can be set.

For example, when the semiconductor device of the present invention isused in a system requiring low power consumption, the generationinterval of the timing pulse signal TPS is elongated and the interval inwhich the temperature is detected is elongated to lower the powerconsumption of the semiconductor device of the present invention.Meanwhile, when the semiconductor device of the present invention isused in a system which takes top priority to a safety operation, thegeneration interval of the timing pulse signal TPS is shortened so thatthe temperature is frequently detected. As a result, the temperaturedetection precision is improved and the erroneous operation of thesemiconductor device of the present invention can be prevented.

In addition, according to the first embodiment, since the tuning codesCC1 to CCn can be rewritten, even when the value is changed after set,the optimal tuning codes CC1 to CCn can be set. For example, when thesimulation result is different from an experiment result, the values ofthe tuning codes CC1 to CCn set based on the simulation result can bereset based on the experiment result.

In addition, the tuning code memory circuit 21 may be a RAM (RandomAccess Memory) having a plurality of memory cells. In this case, theselection circuit 24 outputs an address signal or a control signal tothe tuning code memory circuit 21 based on the selection signal groupSELG, and selects and reads out one of the plurality of tuning codes CC1to CCn from the tuning code memory circuit 21.

In addition, when the values of the tuning codes CC1 to CCn arepreviously adjusted in the manufacturing process of the semiconductordevice of the present invention, variation in characteristics of thememory circuit 40 or the logic circuit 60 caused by a variation inmanufacturing process can be absorbed. For example, variations incharacteristics of the elements in the memory circuit 40 and the logiccircuit 60 are confirmed at the time of wafer test of the semiconductordevice of the present invention, and the values of the tuning codes CC1to CCn are set greater or smaller than the design values as a wholeaccording to the confirmed variations. Thus, the values of the innerpower supply voltages VCCL and VCCM are adjusted according to thevariation in manufacturing process, so that the variation incharacteristics of the memory circuit 40 which is operated by the innerpower supply voltage VCCM and the variation in characteristics of thelogic circuit 60 which is operated by the inner power supply voltageVCCL can be absorbed.

Second Embodiment

Although the number of pulses of the clock signal CLK2 counted while theclock signal CLK1 is counted by N is outputted as the temperature signalTEMP in the semiconductor device according to the first embodiment, thenumber of pulses of the clock signals CLK1 and CLK2 may be counted for apredetermined period of time and a difference between the countednumbers may be outputted as the temperature signal TEMP. A descriptionwill be made of a detection circuit of a temperature T in this casehereinafter.

FIG. 13 is a block diagram showing a constitution of a temperaturedetection circuit 74 according to a second embodiment of the presentinvention. The temperature detection circuit 74 according to the secondembodiment is used instead of the temperature detection circuit 14 inthe semiconductor device according to the first embodiment.

As shown in FIG. 13, the temperature detection circuit 74 includes theabove-described short-cycle oscillators 15 and 16 and a temperaturesignal generation circuit 77. The temperature signal generation circuit77 includes counters 78 and 79 and a subtractor 80, and generates atemperature signal TEMP which is varied according to a temperature T ofthe semiconductor device of the present invention based on the clocksignals CLK1 and CLK2. and outputs it.

The counter 78 counts the number of pulses of the clock signal CLK1while a timing pulse signal TPS is activated and outputs the countednumber N to the subtractor 80. The counter 79 counts the number ofpulses of the clock signal CLK2 while the timing pulse signal TPS isactivated and outputs the counted number M to the subtractor 80. Thesubtractor 80 subtracts the counted number M outputted from the counter79 from the counted number N outputted from the counter 78 and outputs asignal showing its result as the temperature signal TEMP.

FIG. 14 is a timing chart showing an operation of the temperaturedetection circuit 74 according to the second embodiment. As shown inFIG. 14, when the timing pulse signal TPS rises, the short-cycleoscillators 15 and 16 and the counters 78 and 79 are activated. Then,the short-cycle oscillators 15 and 16 oscillate and outputs the clocksignals CLK1 and CLK2, respectively, and the counter 78 starts to countthe number of pulses of the clock signal CLK1 and the counter 79 startsto count the number of pulses of the clock signal CLK2. Then, when thetiming pulse signal TPS falls, the short-cycle oscillators 15 and 16stop their operations and the counted numbers at that time are outputtedto the subtractor 80. Then, when the timing pulse signal TPS risesagain, the same operation as the above is repeated.

Thus, according to the temperature detection circuit 74 of the secondembodiment, the number of pulses of each of the clock signals CLK1 andCLK2 is counted for a predetermined period and the difference betweenthe counted numbers N and M is outputted as the temperature signal TEMP.Therefore, it is necessary for the temperature signal TEMP to express apositive or negative value. Thus, the temperature signal TEMP includes aplurality of bits of data and its most significant bit is used as a signshowing a positive or negative value and the other bits are used assigns showing an absolute value of the difference between the countednumbers N and M.

For example, when the most significant bit is “0”, it means a positivevalue and when it is “1”, it means a negative value. In this case, whenthe most significant bit is “0” and at least another bit is “1” in thetemperature signal TEMP, it means that the counted number N is greaterthan the counted number M, and the frequency f1 of the clock signal CLK1is higher than the frequency f2 of the clock signal CLK2.

Meanwhile, when the most significant bit is “1” and at least another bitis “1” in the temperature signal TEMP, it means that the counted numberN is smaller than the counted number M, and the frequency f1 of theclock signal CLK1 is lower than the frequency f2 of the clock signalCLK2. Thus, referring to the graph shown in FIG. 4, when the mostsignificant bit is “0” and at least another bit is “1” in thetemperature signal TEMP, it means that the temperature T is higher thanthe room temperature T0 and when the most significant bit is “1” and atleast another bit is “1” in the temperature signal TEMP, it means thatthe temperature is lower than the room temperature T0. In addition,regarding the bits other than the most significant bit in thetemperature signal TEMP, as its value becomes greater, the differencebetween the temperature T and the room temperature T0 becomes big.Therefore, the present temperature T can be found by previously findingthe relation between the difference between the counted numbers N and M,and the temperature T through simulation and the like and referring tothe temperature signal TEMP.

As described above, according to the temperature detection circuit 74 inthe second embodiment, similar to the temperature detection circuit 14,the temperature signal TEMP which is varied according to the temperatureT of the semiconductor device of the present invention is generatedbased on the clock signal CLK1 having the positive temperaturecharacteristics with respect to the frequency and the clock signal CLK2having the negative temperature characteristics with respect to thefrequency. According to the second embodiment, when the temperature T isvaried, the frequencies of the clock signals CLK1 and CLK2 are varied inthe opposite directions to each other, so that the counted numbers N andM are also varied in the different directions. Therefore, thetemperature signal TEMP according to the second embodiment is alsosensitively varied with respect to the temperature T. As a result, thetemperature detection precision is improved.

In addition, when the temperature detection circuit 74 in the secondembodiment is incorporated in the semiconductor device instead of thetemperature detection circuit 14, the electrical characteristics of thecircuit to be adjusted such as the inner power supply circuit 30 or 50can be adjusted with respect to the temperature T with high precision.As a result, an erroneous operation of the semiconductor device of thepresent invention can be surely prevented.

In addition, according to the temperature detection circuit 14 accordingto the first embodiment, unlike the temperature detection circuit 74according to the second embodiment, since it is not necessary to performthe subtracting operation and not necessary to provide the subtractor80, the circuit size of the temperature detection circuit 14 can bereduced as compared with the temperature detection circuit 74.

Third Embodiment

Although the inner power supply circuits 30 and 50 are provided as thecircuits whose characteristics are adjusted by the tuning circuit 20 inthe first embodiment, the characteristics of the circuit other than theinner power supply circuits 30 and 50 can be adjusted by using thetemperature signal TEMP of the present invention. According to a thirdembodiment, an example of the circuit other than the circuit to beadjusted will be described.

FIG. 15 is a block diagram showing a constitution of a timing generationcircuit 90 whose electrical characteristics can be adjusted according tothe temperature T by the above temperature detection circuit 10 and thetuning circuit 20. In an asynchronous circuit such as a DRAM, aplurality of timing pulse signals having different rising timings fromeach other are needed in general. The timing generation circuit 90generates a plurality of timing pulse signals TPS1 to TPS5 to besupplied to the asynchronous circuit. For example, the timing pulsesignals TPS1 to TPS5 are supplied to the memory circuit 40 comprisingthe DRAM. In addition, the timing generation circuit 90 is formed on thesemiconductor substrate 1 together with the temperature detectioncircuit 10.

As shown in FIG. 15, the timing generation circuit 90 includes m(.gtoreq.2) stages of delay circuits DC1 to DCm and a selection circuit91. The first stage of delay circuit DC1 delays a reference timing pulsesignal RTPS generating at predetermined intervals for a predeterminedperiod and outputs it to the next stage of delay circuit DC2 and to theselection circuit 91. Each of the delay circuits DC2 to DCm delays thesignal of the previous stage of circuit for a predetermined period andoutputs it to the next stage of circuit and also to the selectioncircuit 91. The selection circuit 91 selects any five delay signals fromthe delay signals DS1 to DSm outputted from the delay circuits DC1 toDCm, based on an adjustment signal TNS outputted from the tuning circuit20 and outputs them as the timing pulse signals TPS1 to TPS5,respectively. Therefore, the five timing pulse signals TPS1 to TPS5 havedifferent rising timings from each other.

The selection circuit 91 determines five signals to be outputted fromthe m delay signals DS1 to DSm according to the tuning code shown in theinputted adjustment signal TNS. For example, when the adjustment signalTNS shows the tuning code CC1, the delay signals DS1 to DS5 areoutputted as the timing pulse signals TPS1 to TPS5, and when theadjustment signal TNS shows the tuning code CC2, the delay signals DS2to DS6 are outputted as the timing pulse signals TPS1 to TPS5, and whenthe adjustment signal TNS shows the tuning code CC3, the delay signalsDS3 to DS7 are outputted as the timing pulse signals TPS1 to TPS5. Thus,the timing pulse signals TPS1 to TPS5 corresponding to the temperature Tcan be supplied to the asynchronous circuit such as the DRAM. Therefore,the asynchronous circuit can execute a predetermined function withouterroneous operation by operating based on the timing pulse signals TPS1to TPS5 appropriately adjusted according to the temperature T even whenits operation timing is varied with the temperature T.

Fourth Embodiment

Although the timing generation circuit 90 is provided as the circuit tobe adjusted in the third embodiment, characteristics of a circuit otherthan the timing generation circuit 90 can be adjusted according to thetemperature T. Hereinafter, such circuit example will be described.

FIG. 16 is a block diagram showing a constitution of a clock signalgeneration circuit 95 which generates a reference clock signal RCLKwhich is used in measuring a refresh time in a DRAM. The electricalcharacteristics of the clock signal generation circuit 95 shown in FIG.16 can be adjusted according to the temperature T using the temperaturedetection unit 10 and the tuning circuit 20. In addition, the clocksignal generation circuit 95 is provided in the memory circuit 40configured by the DRAM.

As shown in FIG. 16, the clock signal generation circuit 95 includes abias voltage generation circuit 96 and plural stages of inversioncircuits 151. In the inversion circuits 151 except for the last stage ofinversion circuit 151, a connection point of a drain of a PMOStransistor 151 a and a drain of an NMOS transistor 151 b is connected toa connection point between a gate of a PMOS transistor 151 a and a gateof an NMOS transistor 151 b of the next stage of inversion circuit 151.In the last stage of inversion circuit 151, a signal at a connectionpoint between a drain of a PMOS transistor 151 a and a drain of an NMOStransistor 151 b is outputted as the reference clock signal RCLK andthat connection point is connected to a connection point between a gateof a PMOS transistor 151 a and a gate of an NMOS transistor 151 b of thefirst stage of inversion circuit 151. The reference clock signal RCLK isinputted to a timer (not shown) in the memory circuit 40 which measuresthe refresh time of the DRAM and the timer measures the refresh time bycounting the number of pulses of the reference clock signal RCLK to apredetermined number.

The bias voltage generation circuit 96 generates a bias voltage BV whichis inputted to each of the gates of the NMOS transistors 151 c of theplural stages of inversion circuits 151. The bias voltage generationcircuit 96 can vary the value of the bias BV into n kinds of values andthe n kinds of voltage values correspond to the n tuning codes CC1 toCCn one on one. The bias voltage generation circuit 96 outputs the biasvoltage BV showing the voltage value corresponding to the tuning codeshown in the inputted adjustment signal TNS.

According to the above circuit constitution, the gate voltage of theNMOS transistor 151 c in the inversion circuit 151 is varied with thetemperature T, so that the frequency of the reference clock signal RCLKis also varied according to the temperature T. Therefore, the refreshtime of the DRAM measured by the timer which is operated by receivingthe reference clock signal RCLK is also varied with the temperature T.Thus, the refresh time is appropriately adjusted with the temperature T.

Fifth Embodiment

FIG. 17 is a block diagram showing constitutions of a tuning circuit 20and an inner power supply circuit 30 in a semiconductor device accordingto a fifth embodiment of the present invention. According to thesemiconductor device in the fifth embodiment, an external terminal 500is provided on the semiconductor substrate 1 in the semiconductor deviceaccording to the first embodiment. Although memory information of thetuning code memory circuit 21 is capable of being rewritten by the CPU(not shown) provided on the semiconductor substrate 1 in thesemiconductor device in the first embodiment, memory information of atuning code memory circuit 21 is capable of being rewritten from theoutside of the semiconductor substrate 1 using the external terminal 500in the semiconductor device according to the fifth embodiment.

The external terminal 500 includes a control signal input terminal 500 aand a data input/output terminal 500 b. An external lead terminal (notshown) is provided in the resin package 100 in which the semiconductorsubstrate 1 is housed. The external lead terminal is partially exposedfrom the resin package 100. The external terminal 500 is electricallyconnected to the external lead terminal. A control signal MCS whichcontrols an operation of the tuning code memory circuit 21 is inputtedfrom the outside of the resin package 100 to the control signal inputterminal 500 a. The control signal MCS includes a readout activationsignal which activates the tuning code memory circuit 21 when data isread out from the tuning code memory circuit 21, a write activationsignal which activates the tuning code memory circuit 21 when data iswritten in the tuning code memory circuit 21, an address signal whichdesignates a region to be accessed in memory regions of the tuning codememory circuit 21 and the like. Data WMD to be written in the tuningcode memory circuit 21 is inputted to the data input/output terminal 500b and data RMD read from the tuning code memory circuit 21 is outputtedto the outside of the resin package 100 through the data input/outputterminal 500 b.

Next, a method of setting the tuning code CC1 to CCn using the externalterminal 500 will be described. FIG. 18 is a flowchart showing thetuning code setting method. According to the fifth embodiment, a waferof the semiconductor substrate 1 is tested before it is housed in theresin package 100, and the tuning code CC1 to CCn are set in the tuningcode memory circuit 21 based on the result of the test.

As shown in FIG. 18, in step s1, a plurality of groups each including ncode values of the tuning codes CC1 to CCn to be stored in the tuningcode memory circuit 21 are previously prepared in view of a variation inmanufacturing process and the plurality of groups are stored in a testerwhich performs the wafer test. In general, temperature characteristicsof the circuit to be adjusted such as the inner power supply circuit 30are varied among wafers because of the variation in manufacturingprocess. Therefore, when the code values of the tuning codes CC1 to CCnare the same among wafers, the electrical characteristics of the circuitto be adjusted could not be sufficiently adjusted using the temperaturesignal TEMP. Then, in view of the variation in manufacturing process,the groups of the code values of the tuning codes CC1 to CCn arepreviously prepared and the group of the code values according to theactual temperature characteristics of the circuit to be adjusted isselected from those to be used.

FIG. 19 is a graph showing that temperature characteristics of thereference voltage generation circuit 31 are varied due to the variationin manufacturing process. The horizontal and vertical axes designate atemperature T and a reference voltage VREF, respectively in FIG. 19. Asshown in FIG. 19, the temperature characteristics of the referencevoltage generation circuit 31 with respect to the reference voltage VREFare varied due to the variation in manufacturing process, and they rangefrom P1 to Px (x.gtoreq.2), for example. According to the fifthembodiment, as shown in FIG. 20, groups of the code values correspondingto the characteristics P1 to Px are prepared. In FIG. 20, n code valuesof the tuning codes CC1 to CCn corresponding to the characteristics PI(I is variable and 1.1toreq.I.Itoreq.x) are set to the code values CV1-Ito CVn-I, respectively. In addition, the graph shown in FIG. 19 can beobtained from a simulation result or an actual measured result.

Referring to FIG. 18, the wafer of the semiconductor substrate 1 onwhich the temperature detection unit 10, the tuning circuit 20 and thelike are formed is tested using a tester in step s2. Then, one group isselected from the groups of the code values prepared in step s1 in thetester according to the result of the wafer test in step s3. Forexample, in step s1, regarding a specific element such as an MOStransistor formed on the semiconductor substrate 1, a correspondingrelation between electrical characteristics of the specific element andcharacteristics P1 to Px in the reference voltage generation circuit 31is obtained, and based on the corresponding relation and a correspondingrelation between the characteristics P1 to Px and the code values shownin FIG. 20, a table showing a corresponding relation between theelectrical characteristics of the specific element and the groupincluding the code values is formed and it is stored in the tester.Then, the electrical characteristics of the specific element is measuredat the time of the wafer test in step s2, and the group of the codevalues corresponding to the measured result is selected form the abovetable in step s3.

Then, in step s4, the tester inputs the write activation signal and theaddress signal to the control signal input terminal 500 a of theexternal terminal 500 and inputs the plurality of code values in theselected group to the data input/output terminal 500 b thereof, andwrites the code values in the tuning code memory circuit 21. Thereference voltage generation circuit 31 is controlled using that tuningcodes CC1 to CCn, so that the reference voltage VREF can beappropriately controlled according to the temperature T without beingaffected by the variation in manufacturing process.

As described above, according to the semiconductor device in the fifthembodiment, since the plurality of tuning codes CC1 to CCn to adjust theelectrical characteristics of the circuit to be adjusted are stored inthe tuning code memory circuit 21 in which the memory information iscapable of being rewritten, the tuning codes CC1 to CCn is capable ofbeing rewritten. Thus, even when the electrical characteristics of thecircuit to be adjusted are varied due to the variation in manufacturingprocess, the values of the tuning codes CC1 to CCn are capable of beingappropriately rewritten according to the variation. Thus, the electricalcharacteristics of the circuit to be adjusted are capable of beingappropriately adjusted based on the temperature detection result withoutbeing affected by the variation in manufacturing process.

In addition, according to the fifth embodiment, since the externalterminal 500 to rewrite the memory information of the tuning code memorycircuit 21 from the outside of the semiconductor substrate 1 isprovided, the tuning codes CC1 to CCn are capable of being directlyrewritten without using a circuit such as the CPU on the semiconductorsubstrate 1. For example, the tuning codes CC1 to CCn can be rewrittenby a device provided outside the resin package 100 or when anothersemiconductor substrate different from the semiconductor substrate 1 isprovided in the resin package 100, the tuning codes CC1 to CCn can berewritten by a circuit formed on the other semiconductor substrate.Furthermore, on the wafer of the semiconductor substrate 1 before housedin the resin package 100, the tuning codes CC1 to CCn are capable ofbeing rewritten by the tester which performs the wafer test.

Sixth Embodiment

FIG. 21 is a circuit diagram showing a constitution of a referencevoltage generation circuit 31 according to a sixth embodiment. Accordingto the sixth embodiment, one example of a circuit constitution of thereference voltage generation circuit 31 will be described.

As shown in FIG. 21, the reference voltage generation circuit 31includes a constant current circuit 310 and n PMOS transistors 311 and(n−1) switch circuits 312. A gate of the PMOS transistor 311 isconnected to the ground voltage and each of the PMOS transistors 311serves as a resistor element. Thus, the plurality of PMOS transistors311 are connected in series with each other and a source terminal of thePMOS transistor 311 at one end is connected to the constant currentcircuit 310 and a drain terminal of the PMOS transistor 311 at the otherend is connected to the ground voltage.

The (n−1) switch circuits 312 are provided so as to correspond to the(n−1) PMOS transistors 311 one on one except for the PMOS transistor 311whose drain terminal is grounded, and each switch circuit 312 isconnected to the corresponding PMOS transistor 311 in parallel. Thus,the switch circuit 312 is turned on or off by an adjustment signal TNSindividually.

According to the reference voltage generation circuit 31 having theabove constitution, a constant current I flows from the source terminalof the PMOS transistor 311 connected to the constant current circuit 310to the drain terminal of the PMOS transistor 311 connected to the groundvoltage. Thus, a voltage which is in proportion to a resistance value ofa path in which the constant current I flows is generated at the sourceterminal of the PMOS transistor 311 connected to the constant currentcircuit 310, and this voltage is outputted as a reference voltage VREF.

In the reference voltage generation circuit 31, the number of the switchcircuits 312 which are turned on according to the value of theadjustment signal TNS is varied. As a result, the resistance value ofthe path in which the constant current I flows is varied in n stages.Thus, the voltage value of the reference voltage VREF is also varied inn stages.

As described above, according to the reference voltage generationcircuit 31 in the sixth embodiment, since the resistance value of thepath in which the constant current I flows can be varied by the numberof the switch circuits 312, the value of the reference voltage VREF canbe simply and finely controlled. When the reference voltage generationcircuit 31 is provided in the inner power supply circuit 30, thereference voltage VREF can be varied according to a temperature signalTEMP. As a result, the value of the inner power supply voltage VCCM canbe appropriately adjusted according to the temperature T of thesemiconductor device of the present invention.

In addition, although the tuning codes CC1 to CCn are stored in thememory circuit in which the memory information can be rewritten in theabove embodiment, when it is not necessary to change the set tuningcodes CC1 to CCn, the tuning codes CC1 to CCn may be stored in a memorycircuit in which memory information cannot be rewritten like a mask ROM.

In addition, although the inner power supply circuits 30 and 50 arestep-down power supply circuits in the above embodiment, they may bestep-up power supply circuits. Furthermore, although both memory circuit40 and logic circuit 60 are formed on the semiconductor substrate 1 inthe above embodiment, only either one may be formed on the semiconductorsubstrate 1. In this case, either one of the inner power supply circuit30 or 50 is to be formed on the semiconductor substrate 1.

While the invention has been shown and described in detail, theforegoing description is in all aspects illustrative and notrestrictive. It is therefore understood that numerous modifications andvariations can be devised without departing from the scope of theinvention.

1.-8. (canceled)
 9. A semiconductor device comprising: a temperaturedetection circuit generating a first clock signal and a second clocksignal, and comprising a temperature signal generation unit thatgenerates a temperature signal which is varied according to atemperature of said semiconductor device based on said first and secondclock signals, said temperature signal generation unit including: afirst counter counting the number of pulses of said first clock signalto a predetermined number and outputting a signal activated while thenumber is counted, and a second counter counting the number of pulses ofsaid second clock signal while said signal outputted from said firstcounter is activated and outputting a signal showing the counted numberas said temperature signal.
 10. The semiconductor device according toclaim 9, wherein the temperature detection circuit further comprises afirst oscillator that generates the first clock signal and a secondoscillator that generates the second clock signal.
 11. The semiconductordevice according to claim 10, wherein the first clock signal haspositive temperature characteristics with respect to a frequency and thesecond clock signal has negative temperature characteristics withrespect to a frequency.
 12. The semiconductor device according to claim9, further comprising: a control circuit sequentially generating aplurality of pulse signals and outputting them to the temperaturedetection circuit, wherein said temperature detection circuit generatessaid temperature signal every time said pulse signal is inputted. 13.The semiconductor device according to claim 9, further comprising: atuning circuit adjusting electrical characteristics of an object circuitbased on said temperature signal; a memory circuit storing a pluralityof tuning codes for adjusting said electrical characteristics of saidobject circuit; inner power supply circuits receiving an adjustmentsignal from the tuning circuit so as to adjust the electricalcharacteristics; and a logic circuit operated by the inner power supplycircuits and executing various logical operations, wherein the tuningcircuit, the memory circuit, the inner power supply circuits, and thelogic circuit are formed on a single semiconductor substrate.